The spec sublanguage is used to specify properties or requirements for the circuit. A standard spec directive has the following syntax:

spec {
    directive_name (sig1, sig2, ...)
    directive_name (sig1, sig2, ...)
    ...
}

There are four exclusive directives, two for exclusive high and two for exclusive low. The directive

 spec {
   exclhi (a,b)
 }

states that the signals a and b will not be true (high) simultaneously, and this is guaranteed by the production rules in the circuit. Violations of this requirement can be detected by actsim when it is run with the -m option.

To simplify modeling of arbiters that cannot be modeled purely at the digital level of abstraction, we include a specific directive that we call “make exclusive high”.

spec {
  mk_exclhi(a,b)
 }

This forces the signals a and b to be exclusive high in the digital simulation model.

There are symmetric variations (excllo and mk_excllo) for exclusive low constraints.

The directive rand_init is used to let the simulator know that a signal might be undefined on power-up, but will initialize to either 0 or 1 at random. The directive hazard is used to let the simulator know that a particular signal can have a switching hazard.

There are two types of timing directives: constraints, and tick specifiers on timing edges.

Asynchronous circuits oscillate, and each oscillation can be viewed as an iteration of the circuit. For timing analysis, it is important to indicate connections from one iteration to the next—i.e. when a signal transition from the current indication leads to a transition from the next iteration. Such directives can be computed during logic synthesis, and ACT expects all logic synthesis tools to emit these directives along with the gate-level implementation.

spec {
   timing a+ -> c-
 }

This directive says that a+ on a particular iteration directly leads to c- in the next iteration. (Sometimes these are called ticked edges in the timing graph.¹⁾²⁾

Timing constraints in ACT are specified using timing forks. Timing forks are used to specify a point of divergence relative timing constraint. The constraint

spec {
  timing a+ : b- < c+
}

states that after a makes a zero-to-one transition, b makes a one-to-zero transition before c makes a zero-to-one transition. a+ is the root of the timing fork, b- is the fast leg of the fork, and c+ is the slow leg of the fork.

spec {
  timing a+ : b- < [15] c+
}

This specifies that the timing fork has a margin of 15 delay units. The conversion from delay units to actual time uses the prs2net.conf configuration parameter net.delay.

If a circuit violates a timing fork, that is an error that is flagged by the ACT simulation tools. During the implementation flow, these timing forks have to be checked. If they are violated, then the circuit must be adjusted to ensure that they are satisfied. There are two ways to satisfy a fork: (i) make the slow path faster; or (ii) make the fast path slower. Adding delays to a fast path is one way to satisfy a timing fork, but that may result in slowing down the circuit. Hence, the default optimizations will attempt to make the slow path faster.

In some cases, a user may want the circuit synthesis and optimization tools to insert the appropriately sized delay line to make the fast path slower. In other words, rather than manually specifying the delay line, a timing fork can be specified where the implementation flow should just add the appropriately sized, technology-dependent delay line. In such cases, a timing fork can be specified as follows:

spec {
  timing a+ : b- << [15] c+
}

This has the same meaning as the earlier fork, except that the tools are provided with a hint that says that it is okay to add delays to correct any violations of this fork.

Finally, timing forks may relate transitions from adjacent iterations.

spec {
  timing a+ : b*- < c+
}

The * indicates that the b- transition is from the following iteration. The * indicator can appear on any signal except the root of the timing fork (in this case a+).

When computing conservative approximations to timing graphs, ACT may add extra edges to the timing graph that are in fact not present in the true timing graph for the system. This can occur, for example, when a gate is modified to incorporate extra signals to simplify the circuit implementation but the new input has no bearing on event causality in the asynchronous circuit. If the automated timing graph construction algorithm includes such edges, they can be explicitly deleted using the following directive:

spec {
   timing a- #> c+
 }

This directive says that the a- to c+ edge should be deleted from the timing graph.