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Static Timing and Power Analysis
ACT includes a static timing and power analysis engine called Cyclone. Cyclone takes an ACT design along with a Liberty file as well as (optional) parasitics to estimate the performance of the circuit, as well as to check any timing constraints required for correct operation.
Timing
Asynchronous circuits contain cycles of gates. How do we time them? The following provides more detail on how static timing analysis for asynchronous circuits works. Please read this before proceeding, as it will explain the terminology used as well as what the interact commands below are for.
Note that timing analysis requires that the design has been mapped to cells.
Reading in Liberty files
The following two commands are used to read in the Liberty (.lib) files for the cells in the design. The timer uses a Liberty file handle to refer to one complete set of characterized cells (at one corner). If your Liberty files are split into say one file per cell, then they can be merged into a single file handle using the commands below.
| Command | Meaning |
|---|---|
| timer:lib-read <file> | This reads in the specified file name as a .lib Liberty file, which contains delay and power information for the cells used in the design. This returns a handle to the Liberty file, used in other timing commands to refer to the .lib. |
| timer:lib-merge <lib> <file> | If your .lib file is split into multiple files (e.g. for different groups of cells), then this command can be used to combine them into one handle. <lib> is a valid Liberty file handle, and <file> is the new Liberty file to be merged into the file handle. |
Creating the timing graph
There are two ways to create a timing graph:
- When the design is fully specified in ACT and production rules are specified using cells that are auto-extracted by the ACT tools (e.g. using the
ckt:cell-mapcommand), the timing arcs from each cell are computed from the production rules directly. These arcs are checked against the.libfile, and an error is reported if the timing arc is missing from the.lib. - When the design has user-specified cells/black box cells, then ACT assumes that timing arcs could potentially relate any input pin of the cell to any output pin, and the arcs are computed based on those specified in the
.libfile.
Delays and transition times are added to the timing graph using information in the .lib file. If you are making your own cells, the ACT tools also include xcell, a cell library characterizer.