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Static Timing and Power Analysis
ACT includes a static timing and power analysis engine called Cyclone. Cyclone takes an ACT design along with a Liberty file as well as (optional) parasitics to estimate the performance of the circuit, as well as to check any timing constraints required for correct operation.
Timing
Asynchronous circuits contain cycles of gates. How do we time them? The following provides more detail on how static timing analysis for asynchronous circuits works. Please read this before proceeding, as it will explain the terminology used as well as what the interact commands below are for.
Note that timing analysis requires that the design has been mapped to cells.
| Command | Meaning |
|---|---|
| timer:lib-read <file> | This reads in the specified file name as a .lib Liberty file, which contains delay and power information for the cells used in the design. This returns a handle to the Liberty file, used in other timing commands to refer to the .lib. |
| timer:lib-merge <lib> <file> | If your .lib file is split into multiple files (e.g. for different groups of cells), then this command can be used to combine them into one handle. <lib> is a valid Liberty file handle, and <file> is the new Liberty file to be merged into the file handle. |