Asynchronous VLSI and Architecture
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Publications organized by research area are listed with pages describing the area. Note that publications are provided here only to ensure timely dissemination of technical work on a non-commercial basis. Copyright are maintained by the authors or by other copyright holders. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

[Papers]  [Theses]  [Reports]
Refereed Papers:

By Date: [click to toggle all vs five]

Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, and Maya Gokhale. Designing an energy-efficient fully-asynchronous deep learning convolution engine. Late breaking results, Design Automation and Test in Europe (DATE), 2024.

Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, and Hai Helen Li. Neuro-symbolic computing: advancements and challenges in hardware-software co-design. IEEE Transactions on Circuits and Systems II (TCAS II), 2023.

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, and Rick Taylor. Toward Carbon-Aware Networking. ACM SIGENERGY Energy Informatics Review (EIR), October 2023.

Rajit Manohar and Yoram Moses. Timed Signaling Processes. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)   — Best paper award

Xiang Wu and and Rajit Manohar. Verification-driven Design for Asynchronous VLSI. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)

Neuroscience and Computing [click to toggle all vs five]

Prafull Purohit, Johannes Leugering, and Rajit Manohar. An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)

Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf)   — Best paper award   — IEEE Micro Top Picks

Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023.    — ISCA-50 25-year retrospective

Ioannis Karageorgos, Karthik Sriran, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Special issue from the HotChips 2022 conference, 2023.

Prafull Purohit and Rajit Manohar. Field-programmable encoding for address-event representation. Frontiers in Neuroscience, 16, December 2022. (pdf)

Design Methodology and Automation [click to toggle all vs five]

Rajit Manohar and Yoram Moses. Timed Signaling Processes. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)   — Best paper award

Xiang Wu and and Rajit Manohar. Verification-driven Design for Asynchronous VLSI. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)

Karthi Srinivasan, Yoram Moses, and Rajit Manohar. Opportunistic Mutual Exclusion. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)   — Best paper nominee

Rajit Manohar. xcell: a library characterizer for combinational and state-holding gates. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2022. (pdf)

Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10):3452--3465 (TCAD), October 2022. (pdf)

Energy-efficient VLSI [click to toggle all vs five]

Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, and Maya Gokhale. Designing an energy-efficient fully-asynchronous deep learning convolution engine. Late breaking results, Design Automation and Test in Europe (DATE), 2024.

Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, and Hai Helen Li. Neuro-symbolic computing: advancements and challenges in hardware-software co-design. IEEE Transactions on Circuits and Systems II (TCAS II), 2023.

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, and Rick Taylor. Toward Carbon-Aware Networking. ACM SIGENERGY Energy Informatics Review (EIR), October 2023.

Eve Schooler, Rick Taylor, Noa Zilberman, Robert Soulé, Dawn Nafus, Rajit Manohar, and Uri Cummings. A Perspective on Carbon-aware Networking. Internet Architecture Board Workshop on Environmental Impact of Internet Applications and Systems, December 2022. (pdf)

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, Rick Taylor. Toward Carbon-Aware Networking. HotCarbon 2022: 1st Workshop on Sustainable Computer Systems Design and Implementation, July 2022. (pdf)

Asynchronous FPGAs [click to toggle all vs five]

Prafull Purohit and Rajit Manohar. Field-programmable encoding for address-event representation. Frontiers in Neuroscience, 16, December 2022. (pdf)

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.

Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.

Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf)

Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf)   — Best paper nominee

Ultra Low Power Embedded Systems [click to toggle all vs five]

Prafull Purohit, Johannes Leugering, and Rajit Manohar. An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf)

Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf)   — Best paper award   — IEEE Micro Top Picks

Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023.    — ISCA-50 25-year retrospective

Ioannis Karageorgos, Karthik Sriran, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Special issue from the HotChips 2022 conference, 2023.

Prafull Purohit and Rajit Manohar. Hierarchical Token Rings for Address-Event Encoding. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf)

Asynchronous Computer Architecture [click to toggle all vs five]

Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf)   — Best paper award   — IEEE Micro Top Picks

Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023.    — ISCA-50 25-year retrospective

Ioannis Karageorgos, Karthik Sriran, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Special issue from the HotChips 2022 conference, 2023.

Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé. Zerializer: Towards Zero-Copy Serialization. 18th Workshop on Hot Topics in Operating Systems (HotOS), May/June 2021. (abstract, pdf)

Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf)

Three Dimensional Integration [click to toggle all vs five]

Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf)

T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract)

S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012.

Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf)

David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf)

Resilient Asynchronous Systems [click to toggle all vs five]

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf)

Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.

Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.

Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf)

Theses:

Ph.D.
Ruslan Dashkin. Asynchronous RISC-V CPU Design with Pre-Silicon Validation on Synchronous FPGAs. Ph.D. thesis, March 2024.

Xiang Wu. Formal Verification of an Asynchronous VLSI Flow. Ph.D. thesis, June 2023.

Prafull Purohit. Asynchronous Circuits for Event-based Computing, Communication, and Sensing. Ph.D. thesis, May 2023.

Yihang Yang. Custom Cell Design Placement Automation for Asynchronous VLSI. Ph.D. thesis, February 2022.

Rui Li. Pipelined Asynchronous High Level Synthesis for General Programs. Ph.D. thesis, December 2021.

Edward Bingham. Self-Timed Length-Adaptive Arithmetic. Ph.D. thesis, December 2020.

Wenmian Hua. Cyclone: The first integrated timing and power engine for asynchronous systems. Ph.D. thesis, May 2020.

Tayyar Rzayev. Architectures for Intelligent Information Systems. Ph.D. thesis, May 2019.

Benjamin Hill. Architecture and Synthesis for Dynamically Reconfigurable Asynchronous FPGAs. Ph.D. thesis, December 2015.

Robert Karmazin. Automating the Physical Design of Asynchronous Circuits. Ph.D. thesis, November 2015.

Jonathan Tse. A Study of Asynchronous Links and Logic. Ph.D. thesis, October 2015.

Stephen Longfield. Constructive Verification of Quasi Delay-Insensitive Circuits. Ph.D. thesis, March 2015.

Carlos Tadeo Ortega Otero. Asynchronous Design for Ubiquitous Computing. Ph.D. thesis, July 2014.

Sandra Jackson. Gradual Synchronization. Ph.D. thesis, July 2014.

Nabil Imam. Canonical Neural Computations in Asynchronous Neuromorphic Circuits. Ph.D. thesis, April 2014.

Benjamin Zhong Xian Tang. Exploiting Asynchrony in GPS Receiver Systems to Enable Ultra-Low-Power Operation. Ph.D. thesis, January 2014.

Basit Riaz Sheikh. Operand-Optimized Asynchronous Floating-Point Arithmetic. Ph.D. thesis, August 2011.

Filipp Akopyan. Hybrid Synchronous/Asynchronous Design. Ph.D. thesis, April 2011.

Christopher LaFrieda. Relaxed Quasi Delay-Insensitive Circuits. Ph.D. thesis, December 2009.

David Fang. A Profiling Infrastructure for Performance Evaluation of Asynchronous Systems. Ph.D. thesis, May 2008.

David Biermann. A Workload Adaptive Voltage Scaling Multiple Clock Domain Architecture. Ph.D. thesis, September 2006.

Song Peng. Implementing Self-Healing Behavior in Quasi Delay-Insensitive Circuits. Ph.D. thesis, August 2006.

Clinton Kelly, IV. The Design and Implementation of an Asynchronous Network on a Chip. Ph.D. thesis, July 2005.

Virantha Ekanayake. Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Ph.D. thesis, May 2005.

John Teifel. Fast Prototyping of Asynchronous Logic. Ph.D. thesis, August 2004.

M.S.
Yuan Tian. A Parallel Implementation of Hierarchical Belief Propagation. M.S. thesis, May 2013.

Stephen Longfield. Design and Implementation of a Low Power Asynchronous GPS Baseband Processor. M.S. thesis, March 2013.

Carlos Tadeo Ortega Otero. Static Power Reduction Techniques for Asynchronous Circuits. M.S. thesis, May 2012.

Nabil Imam. A Communication Infrastructure for Multi-Chip Neuromorphic Systems. M.S. thesis, May 2012.

Christopher LaFrieda. Custom-Quality Wire Routing Using Modern Design Rules. M.S. thesis, August 2005.

Filipp Akopyan. Asynchronous Analog-to-Digital Converter for Low Power Applications. M.S. thesis, August 2005.

David Fang. Width-Adaptive and Non-Uniform Access Asynchronous Register Files. M.S. thesis, January, 2004.

Clinton Kelly, IV. Wireless Network Simulation Done Faster than Real Time. M.S. thesis, January, 2003.

Virantha Ekanayake. Asynchronous Dynamic Random Access Memories. M.S. thesis, January, 2003.

David Biermann. Multiprocessor-Enabled Asynchronous Cache Controller. M.S. thesis, January 2003.

John Teifel. Interchip Communication in Asynchronous VLSI Systems. M.S. thesis, May 2002.

Other Technical Reports:

Rajit Manohar and Alain J. Martin. Pipelined Mutual Exclusion and the Design of an Asynchronous Microprocessor. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1017, November 2001.

Rajit Manohar and Mika Nyström. Implications of Voltage Scaling in Asynchronous Architectures. Cornell Computer Systems Lab Technical Report CSL-TR-2001-1013, April 2001.

Rajit Manohar and Mark Heinrich. The Branch Processor Architecture. Cornell Computer Systems Lab Technical Report CSL-TR-1999-1000, November 1999.

Rajit Manohar. Variable-Precision Number Representations for Asynchronous VLSI. Cornell Computer Systems Lab Technical Report CSL-TR-1999-999, September 1999.

Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12.


 
  
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