Asynchronous VLSI and Architecture

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Selected Chips
First HALO prototype. (2020-2021)
Process: 12nm

A programmable brain-computer interface (BCI) processing chip with a collection of custom processing elements, reconfigurable dataflow interconnect, and a RISC-V control processor.
Highlight: the first HALO prototype with multiple processing elements and reconfigurable interconnect.

An open-source ASIC flow for asynchronous logic (first test chip 2020)
Process: 65nm

A stack machine chip implemented using a new open-source ASIC flow for asynchronous logic. Detailed routing and final chip assembly completed using commercial tools.
Highlight: the first demonstration of a true ASIC flow for asynchronous logic, including translation to gates, creation of an asynchronous cell library, automated cell mapping, a new gridded placement engine, and parallel global routing.

HALO: an architecture for brain-computer interfaces (design 2019; chips 4/2020)
Process: 28nm

Control processor (RISC-V ISA) for a brain-computer interface SoC architecture. First tape-out for the project.

AMC: an asynchronous memory compiler (first test chip 2019)
Process: 65nm

An asynchronous SRAM test chip with layout generated using a memory compiler for pipelined asynchronous SRAM.
Highlight: first asynchronous memory compiler. Generates memories that are competitive with foundry memory compilers.

A Continuous-Time IIR Filter (2015-2017)
Process: 65nm

A continuous-time digital IIR filter implemented with analog and digital asynchronous circuits.
Highlight: the first continuous-time (CT) digital infinite impulse response (IIR) filter. Like other CT digital filters, the power consumption depends on the input signal and is bandwidth-adaptive. The project was led by Prof. Yannis Tsividis.

Braindrop: a mixed-signal neuromorphic chip (design 2013-2017; chips 9/2017)
Process: 28nm FDSOI

A mixed-signal neuromorphic chip with a programming model based on the neural engineering framework.
Highlight: The first neuromorphic project where the hardware was designed to be programmed at a high level of abstraction, rather than by programming weights/connectivity/neuron parameters. Record for energy efficiency in terms of energy per effective synaptic operation. The project was led by Prof. Kwabena Boahen, and incorporates lessons from both Neurogrid and TrueNorth.

TrueNorth: a single chip million spiking neuron system (design 2011-2013; chips 2013)
Process: 28nm

A low power million spiking neurons/chip neuromorphic system with scalable communication (joint project with IBM research).
Highlight: First single chip million neuron neuromorphic architecture. Fully digital, deterministic, highly programmable neurons, synapses, and communication with a glueless chip-to-chip network and less than 70mW power. Hybrid QDI and bundled data asynchronous design, with a low frequency clock for 1:1 correspondence to a parallel discrete event software model. 4096 cores and 5.4 billion transistors makes this the largest asynchronous chip, and one of the largest chips ever designed.

GPS baseband (design 2010-2013; chips 8/2013)
Process: 90nm

A low power GPS baseband processor
Highlight: An asymmetric self-timed baseband processor that uses 1.4mW for continuous tracking of 6 channels with 3D RMS error less than four meters.

Split-foundry AFPGA (design 10/2012; chips 2/2013)
Process: 0.13μm split foundry

Design of a chip using split-foundry technology, where the FEOL plus initial metallization is completed at one foundry, with the BEOL completed at a second foundry.
Highlight: The first FPGA (and one of the first complex digital ASICs) in a split-foundry process. The layout of the chip was automatically generated even though the circuits are custom. This was done through dynamic cell generation, rather than technology mapping to standard cells.

Ultra low power embedded processor (design 5/2012; chips 9/2012)
Process: 90nm

Design of a low power microcontroller for embedded systems.
Highlight: Capable of operating at >90MIPS for <5mW in 90nm.

Digital neurosynaptic core (design and chips 2010)
Process: 45nm SOI

A programmable event-driven digital core for neuromorphic systems (joint project with IBM research).
Highlight: a new approach to neuromorphic system design using a cross-bar based synapse organization for increasing synaptic density as well as managing communication fanout.

3D characterization (design 10/2006; chips 9/2007)
Process: 0.18μm SOI + 3D

Characterization of thermals and process variation in Lincoln Labs' 3D process.

Low temperature characterization (design/chips 2007)
Process: 0.5μm SiGe

Demonstration of asynchronous circuit operation from 40K-400K for NASA's Extreme Environment Electronics program.

3D AFPGA (design 4/2005; chips 6/2006)
Process: 0.18μm SOI + 3D

3D asynchronous FPGA with three tiers in Lincoln Labs' 3D process.

SNAP microprocessor (design 2001-2005; chips 6/2005)
Process: 0.18μm

A dual-use asynchronous microprocessor: (i) An ultra low power processor for sensor network applications; (ii) A high-performance wireless network simulator.
Highlight: The first microprocessor for sensor networks.

Asynchronous FPGA (design 2003-2004; chips 6/2004)
Process: 0.18μm

A pipeline-level programmable dataflow asynchronous FPGA (AFPGA).
Highlight: The fastest CMOS FPGA. The first complete tool-chain for asynchronous FPGAs. This technology launched Achronix Semiconductor Corp.

MiniMIPS (design: 1995-1998; chips 1/1999)
Process: 0.6μm
Andrew Lines, Rajit Manohar, Mika Nystrom, Robert Southworth, Paul Penzes, Uri Cummings, Tak-Kwan Lee; Advisor: Alain Martin

A high-performance asynchronous MIPS processor.
Highlight: The fastest asynchronous microprocessor. One of the fastest integer cores (academic or commercial) in 0.6μm