Differences

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--- tools:start [2025/10/08 14:49] – rajit
+++ tools:start [2026/01/18 12:23] (current) – rajit
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 In addition to the core ACT library, we have also implemented a number of tools for asynchronous circuit design. Some of the core tools are included as part of the main Github repository, while others have their own repository. For completeness, we also include links to other open-source tools that can be used to implement different parts of the VLSI flow.
+The tools are in two categories:
+  - The core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.
+  - A few tools (marked with ''(old)'') do not either because they will, over time, be replaced by ACT tools or because their functionality is independent of the ACT library.
+Two useful concepts to keep in mind when using the ACT tools are [[intro_example:name_mangling|expanded names and mangled names]].
+===== Simulation =====
+We use a combination of our own simulators as well as other open-source simulators to verify functionality of our circuits.
    * [[actsim|actsim]]: an ACT simulator.
+   * [[prsim|prsim]]: a digital production-rule simulator ''(old)''
+   * Third-party tools:
+      * [[http://github.com/Xyce|Xyce]]: An analog circuit simulator developed by Sandia National Labs. Note that ''actsim'' can also be linked against the ''Xyce'' library as part of its build process to provide mixed-mode simulation.
+      * [[http://opencircuitdesign.com/irsim/index.html|irsim]]: A switch-level circuit simulator
+===== Format converters =====
+Different VLSI tools use different file formats, and we provide a number of tools to convert between a range of file formats. These can be used to, for example, generate industry-standard formats from ACT or to import third-party designs into ACT.
    * [[netgen|prs2net]]: a production rule to SPICE netlist generator
    * [[prs2sim|prs2sim]]: a production rule to sim file converter
    * [[ext2sp|ext2sp]]: converts magic extract files into a hierarchical spice file
-   * [[pgen|pgen]]: a parser generator used to emit the ACT parser. Used internally.
+   * [[act2lef|act2lef]]: Generate LEF/DEF from an ACT design
+   * [[act2v|act2v]]: Convert ACT file into a Verilog netlist. Note this is only useful for converting netlists in ACT format to Verilog format.
+   * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file
+   * aflat and prspack: a production rule flattener and compaction tool. See the documentation for [[prsim|prsim]]. ''(old)''
+===== Implementation and verification =====
+These are tools that are useful for translating ACT files into a final implementation in GDS, as well as verifying different aspects of the design.
    * [[tools:layout:|Layout generation]]
    * [[lvp|lvp]]: layout versus production rules
-   * [[act2lef|act2lef]]: Generate LEF/DEF from an ACT design
-   * [[act2v|act2v]]: Convert ACT file into a Verilog netlist
-   * [[adepend|adepend]]: Print dependencies of an ACT file
    * [[chp2prs|chp2prs]]: convert CHP to production rules
    * [[interact|interact]]: Interactive ACT
    * [[prs2cells|prs2cells]]: extract ACT cells needed to implement a design
-   * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file
    * [[asic:timing:xcell:start|xcell]]: Cell library characterizer
+   * [[AMC:|AMC]]: an asynchronous memory compiler ''(old)''
+   * Third-party tools
+      *  [[http://opencircuitdesign.com/magic/index.html|magic]]: The Magic VLSI layout editor
+      * Gemini: a netlist comparison for strict layout-versus-schematic checking {{:tools:gemini-2.7.2.tar.gz|Gemini}}
+      * [[http://opencircuitdesign.com/netgen/index.html|netgen]]: another tool for LVS
-These are core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.
+===== Miscellaneous =====
-Standalone tools:
+The following utilities are also provided as part of the core ACT repository:
-   * [[prsim|prsim]]: a digital production-rule simulator
-   * aflat and prspack: a production rule flattener and compaction tool. See the documentation for [[prsim|prsim]].
-   * [[AMC:|AMC]]: an asynchronous memory compiler
+   * [[pgen|pgen]]: a parser generator used to emit the ACT parser. Used internally.
+   * [[adepend|adepend]]: Print dependencies of an ACT file suitable for use in a ''Makefile''
-External open-source tools:
-   * [[http://github.com/Xyce|Xyce]]: An analog circuit simulator developed by Sandia National Labs
-   * [[http://opencircuitdesign.com/magic/index.html|magic]]: The Magic VLSI layout editor
-   * [[http://opencircuitdesign.com/irsim/index.html|irsim]]: A switch-level circuit simulator
-   * Layout versus schematic (LVS) checking:
-      * Gemini: a netlist comparison for strict layout-versus-schematic checking {{:tools:gemini-2.7.2.tar.gz|Gemini}}
-      * [[http://opencircuitdesign.com/netgen/index.html|netgen]]: another tool for LVS
-Two useful concepts to keep in mind when using the ACT tools are [[intro_example:name_mangling|expanded names and mangled names]].