Differences

This shows you the differences between two versions of the page.

--- tools:start [2023/04/07 12:53] – rajit
+++ tools:start [2026/04/18 16:15] (current) – [Implementation and verification] rajit
@@ Line 3: / Line 3: @@
 In addition to the core ACT library, we have also implemented a number of tools for asynchronous circuit design. Some of the core tools are included as part of the main Github repository, while others have their own repository. For completeness, we also include links to other open-source tools that can be used to implement different parts of the VLSI flow.
+The tools are in two categories:
+  - The core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.
+  - A few tools (marked with ''(old)'') do not either because they will, over time, be replaced by ACT tools or because their functionality is independent of the ACT library.
+Two useful concepts to keep in mind when using the ACT tools are [[intro_example:name_mangling|expanded names and mangled names]].
+===== Simulation =====
+We use a combination of our own simulators as well as other open-source simulators to verify functionality of our circuits.
    * [[actsim|actsim]]: an ACT simulator.
+   * [[prsim|prsim]]: a digital production-rule simulator ''(old)''
+   * Third-party tools:
+      * [[http://github.com/Xyce|Xyce]]: An analog circuit simulator developed by Sandia National Labs. Note that ''actsim'' can also be linked against the ''Xyce'' library as part of its build process to provide mixed-mode simulation.
+      * [[http://opencircuitdesign.com/irsim/index.html|irsim]]: A switch-level circuit simulator
+===== Format converters =====
+Different VLSI tools use different file formats, and we provide a number of tools to convert between a range of file formats. These can be used to, for example, generate industry-standard formats from ACT or to import third-party designs into ACT.
    * [[netgen|prs2net]]: a production rule to SPICE netlist generator
    * [[prs2sim|prs2sim]]: a production rule to sim file converter
    * [[ext2sp|ext2sp]]: converts magic extract files into a hierarchical spice file
-   * [[lvp|lvp]]: layout versus production rules
+   * [[act2lef|act2lef]]: Generate LEF/DEF from an ACT design
+   * [[act2v|act2v]]: Convert ACT file into a Verilog netlist. Note this is only useful for converting netlists in ACT format to Verilog format; the Verilog itself is structural, and doesn't contain translations of language bodies.
+   * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file
+   * aflat and prspack: a production rule flattener and compaction tool. See the documentation for [[prsim|prsim]]. ''(old)''
-These are core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.
+===== Implementation and verification =====
+These are tools that are useful for translating ACT files into a final implementation in GDS, as well as verifying different aspects of the design.
+   * [[.interact:start|interact]]: Interactive ACT: this is the main tool for the ACT flow. It includes enough functionality to implement many of the standalone tools, including ''prs2cells'', ''prs2net'', ''prs2sim'', ''act2v'', and ''act2lef''. In addition, it is used for the [[asic:start|ACT ASIC flow]].
+   * [[tools:layout:|Layout generation]]
+   * [[lvp|lvp]]: layout versus production rules
+   * [[chp2prs|chp2prs]]: convert CHP to production rules
+   * [[prs2cells|prs2cells]]: extract ACT cells needed to implement a design
+   * [[asic:timing:xcell:start|xcell]]: Cell library characterizer
+   * [[AMC:|AMC]]: an asynchronous memory compiler ''(old)''
+   * [[fpga|FPGA mapping]]: tools to translate ACT into a simulation model for prototyping on standard FPGAs.
-Standalone tools:
+Third-party tools:
-   * [[prsim|prsim]]: a digital production-rule simulator
+      *  [[http://opencircuitdesign.com/magic/index.html|magic]]: The Magic VLSI layout editor
-   * aflat and prspack: a production rule flattener and compaction tool. See the documentation for [[prsim|prsim]].
+      * Gemini: a netlist comparison for strict layout-versus-schematic checking {{:tools:gemini-2.7.2.tar.gz|Gemini}}
-   * [[AMC:|AMC]]: an asynchronous memory compiler
+      * [[http://opencircuitdesign.com/netgen/index.html|netgen]]: another tool for LVS
+===== Miscellaneous =====
-External open-source tools:
+The following utilities are also provided as part of the core ACT repository:
-   * [[http://github.com/Xyce|Xyce]]: An analog circuit simulator developed by Sandia National Labs
-   * [[http://opencircuitdesign.com/magic/index.html|magic]]: The Magic VLSI layout editor
-   * [[http://opencircuitdesign.com/irsim/index.html|irsim]]: A switch-level circuit simulator
-   * Gemini: a netlist comparison for strict layout-versus-schematic checking {{:tools:gemini-2.7.2.tar.gz|Gemini}}
-===== Expanded names =====
+   * [[pgen|pgen]]: a parser generator used to emit the ACT parser. Used internally.
+   * [[adepend|adepend]]: Print dependencies of an ACT file suitable for use in a ''Makefile''
-A concept one should be familiar with, especially when debugging and/or understanding error messages is the notion of expanded names. This is best illustrated with an example. Consider the following templated process definition:
-<code act>
-template<pint A; pbool B; pint C[A]> defproc example(...) { ... }
-example<1+1,true,{1,5}> e1;
-example<1,false,{2}> e2;
-</code>
-The type of the process defined is ''example'', but the instances ''e1'' and ''e2'' include specific template parameters. After the design is expanded and all template parameters are substituted, different variations of ''example'' are created for ''e1'' and ''e2''. These //expanded// versions of types are given different names within the ACT framework.  In particular, the expanded type for ''e1'' would be ''example<2,t,{1,5}>'' (here ''t'' is used as a stand-in for the value of the Boolean parameter ''true'').  If ''example'' did not take on any template parameters, the expanded version of the type would be named ''example<>''.