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tools:start [2023/06/23 11:23]
rajit [Tools]
tools:start [2024/07/24 14:07] (current)
rajit [Tools]
Line 10: Line 10:
    * [[tools:layout:|Layout generation]]    * [[tools:layout:|Layout generation]]
    * [[lvp|lvp]]: layout versus production rules    * [[lvp|lvp]]: layout versus production rules
 +   * [[act2lef|act2lef]]: Generate LEF/DEF from an ACT design
 +   * [[act2v|act2v]]: Convert ACT file into a Verilog netlist
 +   * [[adepend|adepend]]: Print dependencies of an ACT file
 +   * [[chp2prs|chp2prs]]: convert CHP to production rules
 +   * [[interact|interact]]: Interactive ACT
 +   * [[prs2cells|prs2cells]]: extract ACT cells needed to implement a design
 +   * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file
 +   * [[asic:timing:xcell:start|xcell]]: Cell library characterizer
  
 These are core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides. These are core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.