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tools:start [2024/07/24 18:07] – [Tools] rajittools:start [2024/07/24 18:07] (current) – [Tools] rajit
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    * [[prs2cells|prs2cells]]: extract ACT cells needed to implement a design    * [[prs2cells|prs2cells]]: extract ACT cells needed to implement a design
    * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file    * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file
-   * [[xcell|xcell]]: Cell library characterizer+   * [[asic:timing:xcell:start|xcell]]: Cell library characterizer
  
 These are core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides. These are core ACT tools--i.e. tools that use the core ACT library and take ACT files as input. They also accept the standard ACT [[:stdoptions:start|command-line arguments]], in addition to their own arguments. The standard ACT options include ways to specify technology-specific information, as well as local configuration overrides.