| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| tools:start [2026/03/12 05:49] – [Implementation and verification] rajit | tools:start [2026/09/25 11:11] (current) – [Miscellaneous] rajit |
|---|
| * [[ext2sp|ext2sp]]: converts magic extract files into a hierarchical spice file | * [[ext2sp|ext2sp]]: converts magic extract files into a hierarchical spice file |
| * [[act2lef|act2lef]]: Generate LEF/DEF from an ACT design | * [[act2lef|act2lef]]: Generate LEF/DEF from an ACT design |
| * [[act2v|act2v]]: Convert ACT file into a Verilog netlist. Note this is only useful for converting netlists in ACT format to Verilog format. | * [[act2v|act2v]]: Convert ACT file into a Verilog netlist. Note this is only useful for converting netlists in ACT format to Verilog format; the Verilog itself is structural, and doesn't contain translations of language bodies. |
| * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file | * [[v2act|v2act]]: Translate a Verilog netlist into an ACT file |
| * aflat and prspack: a production rule flattener and compaction tool. See the documentation for [[prsim|prsim]]. ''(old)'' | * aflat and prspack: a production rule flattener and compaction tool. See the documentation for [[prsim|prsim]]. ''(old)'' |
| These are tools that are useful for translating ACT files into a final implementation in GDS, as well as verifying different aspects of the design. | These are tools that are useful for translating ACT files into a final implementation in GDS, as well as verifying different aspects of the design. |
| |
| * [[.interact:start|interact]]: Interactive ACT: this is the main tool for the ACT flow. It includes enough functionality to implement many of the standalone tools, including ''prs2cells'', ''prs2net'', ''prs2sim'', ''act2v'', and ''act2lef''. | * [[.interact:start|interact]]: Interactive ACT: this is the main tool for the ACT flow. It includes enough functionality to implement many of the standalone tools, including ''prs2cells'', ''prs2net'', ''prs2sim'', ''act2v'', and ''act2lef''. In addition, it is used for the [[asic:start|ACT ASIC flow]]. |
| * [[tools:layout:|Layout generation]] | * [[tools:layout:|Layout generation]] |
| * [[lvp|lvp]]: layout versus production rules | * [[lvp|lvp]]: layout versus production rules |
| * [[asic:timing:xcell:start|xcell]]: Cell library characterizer | * [[asic:timing:xcell:start|xcell]]: Cell library characterizer |
| * [[AMC:|AMC]]: an asynchronous memory compiler ''(old)'' | * [[AMC:|AMC]]: an asynchronous memory compiler ''(old)'' |
| * Third-party tools | * [[fpga|FPGA mapping]]: tools to translate ACT into a simulation model for prototyping on standard FPGAs. |
| | |
| | Third-party tools: |
| * [[http://opencircuitdesign.com/magic/index.html|magic]]: The Magic VLSI layout editor | * [[http://opencircuitdesign.com/magic/index.html|magic]]: The Magic VLSI layout editor |
| * Gemini: a netlist comparison for strict layout-versus-schematic checking {{:tools:gemini-2.7.2.tar.gz|Gemini}} | * Gemini: a netlist comparison for strict layout-versus-schematic checking {{:tools:gemini-2.7.2.tar.gz|Gemini}} |
| * [[pgen|pgen]]: a parser generator used to emit the ACT parser. Used internally. | * [[pgen|pgen]]: a parser generator used to emit the ACT parser. Used internally. |
| * [[adepend|adepend]]: Print dependencies of an ACT file suitable for use in a ''Makefile'' | * [[adepend|adepend]]: Print dependencies of an ACT file suitable for use in a ''Makefile'' |
| | * [[dflow2dot|dflow2dot]]: Generate graphviz ''.dot'' files to visualize dataflow graphs (dataflow sublanguage) |
| | * [[act2dot|act2dot]]: Generate graphviz ''.dot'' files to visualize connectivity in the ACT design. |
| |
| |